Integrated high-frequency MOS oscillator

ABSTRACT

An integrated high-frequency MOS oscillator circuit comprising at least one active element (F 1 ) and a frequency determining circuit, the oscillator circuit further comprising at least one frequency selective network (R 1 , C 1 ) which is built up from one or more resistors and one or more reactive elements, such that the oscillation at the desired oscillator frequency can take place substantially unhampered, while oscillations at parasitic oscillation frequencies are suppressed in that at the parasitic oscillation frequencies the loop gain is reduced to an absolute value less than 1.

The invention relates to an integrated high-frequency MOS oscillatorcircuit, comprising at least one active element and a frequencydetermining circuit.

Such oscillator circuits are already known and are typically, though notnecessarily, implemented as balanced circuits. An example of such a MOSoscillator circuit implemented as a balanced circuit is described in IBMTechnical Disclosure Bulletin Vol. 40, No. 10, October 1997.

MOS transistors are usually applied chiefly in technology controllingand determining circuits such as processors and memories. In this typeof circuits, miniaturization, clock rate and cost price are the mostimportant key issues. The pursuit of these key issues has also led toMOS transistors having become increasingly better useful for analog veryhigh frequency circuits such as oscillators working far into theGigahertz range. The MOS transistor, whose performance in thehigh-frequency signal processing area until recently was considerablypoorer than that of the conventional bipolar transistor, now hascomparable properties, but with less surface area used, which improvesminiaturization. In addition, the low cost price is an advantage.

A problem occurring in modern integrated high-frequency oscillatorsbuilt up with MOS transistors, however, is the occurrence of strongparasitic resonances at one or even more frequencies as a result ofparasitic reactive impedances. These parasitic resonances can be farabove the intended oscillator frequency, for instance in the range of 50to 60 GHz. The danger exists that the oscillator circuit starts tooscillate at these higher frequencies, which is highly undesirable.

Accordingly, there is a need for an improved high-frequency oscillatorcircuit which does not have any parasitic oscillator frequencies andwhich can be built up using MOS elements, while substantiallymaintaining the good properties of the MOS technique.

The object of the invention is to provide for the need outlined andgenerally to make available a reliable MOS oscillator circuit whichexhibits no or substantially no parasitic oscillations. To that end,according to the invention, an oscillator circuit of the above-describedkind is characterized in that the oscillator circuit is further providedwith at least one frequency selective network, which is built up fromone or more resistors and one or more reactive elements, such that theoscillation at the desired oscillator frequency can take placesubstantially unhampered, while osillations at parasitic oscillationfrequencies are suppressed in that at the parasitic oscillationfrequencies the loop gain is reduced to an absolute value less than 1.

In the following, the invention is further described with reference tothe appended drawing.

FIG. 1 schematically shows an example of a known oscillator circuit; and

FIG. 2 schematically shows an example of an oscillator circuit accordingto the invention.

FIG. 1 schematically shows an example of a known integratedhigh-frequency oscillator circuit 1, in this case implemented as abalanced circuit. The oscillator circuit shown is built up using activeMOS elements F1 and F2 which have been formed on a single chip. In thisexample, the elements F1 and F2 are of the FET type and each have threeconnecting electrodes designated D (drain), S (source) and G (gate). Thetwo source electrodes are connected with each other. The gate and drainelectrodes of the two elements F1 and F2 are crosswise connected witheach other, in such a manner that the gate electrode of element F1 isconnected, via a conductor 2 provided on the chip, with the drainelectrode of the other element F2. Similarly, the gate electrode ofelement F2 is connected via a conductor 3 with the drain electrode ofelement F1.

Further, the two drain electrodes are connected with each other via acapacitor C formed on the chip, for instance a varactor. Each of thedrain electrodes, finally, is connected with the end of an associatedcoil L1 and L2, respectively, formed on the chip, the other ends of thecoils L1 and L2 being connected with each other and, directly orindirectly, with an energy source, in this example a power source I.

It is noted that the invention to be described hereinafter can beapplied both in single-ended configurations and balanced configurations.An advantage of the use of a balanced configuration as shown is thatsignals of opposite phase occur therein. As a result, injection ofoscillator signals in the substrate or pickup of noise signals from thesubstrate is suppressed.

In oscillator circuits of the above-described known type, as a result ofparasitic impedances in the coil L1, L2 and/or the capacitor C, strongparasitic oscillation phenomena can arise at frequencies far above theintended oscillation frequency. Depending on the specific structure,this may even involve several parasitic resonance ranges. Such parasiticresonance ranges are highly undesirable because as a result of them theoscillator does not function in the intended manner.

FIG. 2 schematically shows an example of an oscillator circuit 20according to the invention. In FIG. 2, corresponding elements areindicated with the same reference symbols as in FIG. 1. The circuitshown in FIG. 2 differs from that of FIG. 1 in that the gate electrodesare not connected with the drain electrodes of the other active elementsdirectly but via a resistor R1 and R2, respectively. Further, the gateelectrodes are each connected via a capacitor C1 and C2, respectively,to the associated source electrode and hence in this example are alsogrounded. In fact, between the gate electrode of one element and thedrain electrode of the other element a respective RC network isconnected. The RC network forms a first order low-pass filter whichcauses the loop gain to decrease with increasing frequency. The pole ofthe RC network is chosen such that the oscillation at the desiredfrequency is not influenced, but parasitic oscillation at higherfrequencies is prevented.

It is noted that it is not always necessary to especially provide aresistance element and/or capacitive element. In some cases, dependingon the circuit design, it may be possible to make use of an inherentlypresent parasitic gate resistance and/or an inherently present parasiticgate-source capacitance, alone or in combination with an additionalresistor or capacitor. The use of an additional part of the gatematerial as resistance is also possible. To that end, the MOS elementcan optionally be deliberately designed with a special architecture.

Further, it is possible to use differently structured frequencyselective networks, which are included in the gate connections, as longas the loop gain is reduced as little as possible at the desiredoscillation frequency and, conversely, to a sufficient extent at theparasitic frequencies. Such a frequency selective network can, ifdesired, comprise one or more coils but, in view of the dimensions ofcoils, is preferably built up only from resistance elements andcapacitive elements. The circuit shown in FIG. 2 can also be realizedusing PMOS elements, besides NMOS elements.

After the foregoing, these and similar modifications will readily occurto one skilled in the art and are understood to fail within the scope ofthe invention.

1. An integrated high-frequency MOS oscillator circuit comprising: at least one active element; a frequency determining circuit; and wherein the oscillator circuit is further provided with at least one frequency selective network, which is built up from one or more resistors and one or more reactive elements, such that the oscillation at a desired oscillator frequency can take place substantially unhampered, while oscillations at parasitic oscillation frequencies are suppressed in that at the parasitic oscillation frequencies a loop gain is reduced to an absolute value less than
 1. 2. The oscillator circuit according to claim 1, wherein the at least one frequency selective network comprises an RC network.
 3. The oscillator circuit according to claim 1, wherein the at least one frequency selective network comprises at least one parasitic impedance of the at least one active element.
 4. The oscillator circuit according to claim 1, wherein the at least one active element is a MOSFET with a gate electrode, a source electrode and a drain electrode and the frequency selective network comprises a resistor connected with the gate electrode and a capacitor arranged between the gate electrode and the source electrode.
 5. The oscillator circuit according to claim 4, wherein the resistor and/or the capacitor can be at least partly formed by parasitic impedances.
 6. The oscillator circuit according to claim 1, wherein the circuit is implemented as a balanced circuit with crosswise connections between the gate electrode of one active element and the drain electrode of another active element, while a respective frequency selective network is connected between the gate electrode of one active element and the drain electrode of the another active element.
 7. The oscillator circuit according to claim 1, wherein the components of the frequency selective network are at least partly formed by giving a MOS element, in the manufacture thereof, a special architecture.
 8. The oscillator circuit according to claim 2, wherein the RC network comprises a first order low pass filter.
 9. An Integrated high-frequency oscillator circuit for suppressing parasitic oscillator frequencies, the circuit comprising: at least one active element, wherein the at least one active element comprises a gate electrode, a source electrode, and a drain electrode; a frequency determining circuit; at least one frequency selective network comprising at least one resistor and at least one reactive element; and wherein the frequency selective network further comprises the at least one resistor connected with the gate electrode and a capacitor arranged between the gate electrode and the source electrode.
 10. The oscillator circuit of claim 9, wherein the at least one active element is a MOSFET.
 11. The oscillator circuit of claim 9, wherein the resistor and/or the capacitor can be at least formed by parasitic impedances.
 12. The oscillator circuit of claim 9, wherein the at least one frequency selective network comprises an RC network.
 13. The oscillator circuit of claim 12, wherein the RC network comprises a first order low pass filter.
 14. The oscillator circuit of claim 13, wherein the low pass filter causes a loop gain to decrease with increasing frequency.
 15. The oscillator circuit of claim 8, wherein the at least one frequency selective network comprises at least one parasitic impedance of the at least one active element.
 16. The oscillator circuit of claim 8, wherein the oscillator circuit is implemented as a balanced circuit with crosswise connections between the gate electrode of one active element and the drain electrode of another active element, while a respective frequency selective network is connected between the gate electrode of one active element and the drain electrode of the another active element. 